A content addressable memory (CAM) includes an array of CAM cells arranged in rows and columns, in which each row of the CAM array corresponds to a word of stored contents. The CAM cells in a given row connected to a word line and a match line associated with the row. The match line may carry a signal that indicates whether the word stored in the row matches an input search word. A comparator circuit may compare the stored word with the search word and thus produce a match bit signal. The CAM can be classified into binary CAM and trinity CAM according to the number of possible states encoded in the memory cell.
Considering a binary CAM, each CAM cell includes a data memory cell and a comparator circuit. The data memory cell stores a data bit and a complementary data bit, and “0’ and “1” are two possible states stored in each CAM cell. With respect to a trinity CAM, each CAM cell includes a data memory cell, a mask memory cell, and a comparator circuit. The data memory cell stores a data bit and a complementary data bit, and the mask memory cell stores a mask bit and a complementary mask bit. “0’, “1” and “don't care” are three possible states stored in each CAM cell.
Conventionally, when a signal carried in the word line is logic HIGH or “1”, the data bit may be read out of or written into the CAM cell through a bit line. However, the CAM cell may be subject to the “disturbance in word lines” problem, in which no data bit is read or written when the signal in the word line is logic HIGH or “1”. This may cause data damage or fault operation. Consequently, it is in need to develop a new content addressable memory technique.